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ASAP
2004
IEEE
101views Hardware» more  ASAP 2004»
13 years 10 months ago
Register Organization for Enhanced On-Chip Parallelism
Large register file with multiple ports is a critical component of a high-performance processor. A large number of registers are necessary for processing a larger number of in-fli...
Rama Sangireddy
CODES
2004
IEEE
13 years 10 months ago
Power analysis of system-level on-chip communication architectures
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-level on-chip communication architecture is emerging as a significant source of power consumpti...
Kanishka Lahiri, Anand Raghunathan
CF
2006
ACM
13 years 10 months ago
An efficient cache design for scalable glueless shared-memory multiprocessors
Traditionally, cache coherence in large-scale shared-memory multiprocessors has been ensured by means of a distributed directory structure stored in main memory. In this way, the ...
Alberto Ros, Manuel E. Acacio, José M. Garc...
AOSD
2008
ACM
13 years 8 months ago
AJANA: a general framework for source-code-level interprocedural dataflow analysis of AspectJ software
Aspect-oriented software presents new challenges for the designers of static analyses. Our work aims to establish systematic foundations for dataflow analysis of AspectJ software....
Guoqing Xu, Atanas Rountev
IJFCS
2006
130views more  IJFCS 2006»
13 years 6 months ago
Mealy multiset automata
We introduce the networks of Mealy multiset automata, and study their computational power. The networks of Mealy multiset automata are computationally complete. 1 Learning from Mo...
Gabriel Ciobanu, Viorel Mihai Gontineac