49 search results - page 2 / 10 » A Low Power Charge-Recycling CMOS Clock Buffer |
ISCAS
2007
IEEE
13 years 11 months ago
2007
IEEE
— A methodology based on supply voltage optimization for lowering the power consumption and temperature fluctuations induced skew of clock distribution networks is proposed in th...
GLVLSI
2006
IEEE
13 years 11 months ago
2006
IEEE
A sensitivity analysis of resonant H-tree clock distribution networks is presented in this paper for a TSMC 0.18 μm CMOS technology. The analysis focuses on the effect of the dri...
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
- The power dissipation (PT) and delay time (tdT) of a CMOS clock driver were minimized. Eight test circuits, each of which has 2 two-stage clock drivers, and a register array were...
TVLSI
2008
13 years 4 months ago
2008
Recently we proposed a new clocking scheme, injection-locked clocking (ILC), to combat deteriorating clock skew and jitter, and hence reduce power consumption in highperformance mi...
ICCAD
1993
IEEE
13 years 9 months ago
1993
IEEE
