49 search results - page 9 / 10 » A Low Power Charge-Recycling CMOS Clock Buffer |
IOLTS
2005
IEEE
13 years 11 months ago
2005
IEEE
With the aggressive scaling of the CMOS technology parametric variation of the transistor threshold voltage causes significant spread in the circuit delay as well as leakage spect...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
- This paper presents a novel architectural mechanism and a power management structure for the design of an energy-efficient Gigabit Ethernet controller. Key characteristics of suc...
ISCAS
2005
IEEE
13 years 11 months ago
2005
IEEE
Abstract- This paper describes the implementation of an areaefficient and protected user memory-mapped network interface, the pbuf (Parcel Buffer), for the Data IntensiVe Architect...
EUC
2006
Springer
13 years 9 months ago
2006
Springer
- Modern portable or embedded systems support more and more complex applications. These applications make embedded devices require not only low powerconsumption, but also high comp...
ASPDAC
2008
ACM
13 years 7 months ago
2008
ACM
This paper presents a new logic style, named Current-Mode Differential logic (CMDL), that achieves both high operating speed and low power consumption. Inspired by the low-voltage ...