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ISQED
2006
IEEE
132views Hardware» more  ISQED 2006»
13 years 11 months ago
Leakage Biased Sleep Switch Domino Logic
- A low overhead circuit technique is proposed in this paper for simultaneously reducing subthreshold and gate oxide leakage currents in domino logic circuits. PMOS sleep transisto...
Zhiyu Liu, Volkan Kursun
ISLPED
2000
ACM
91views Hardware» more  ISLPED 2000»
13 years 9 months ago
High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies
A new high-speed Domino circuit, called HS-Domino is developed. HS-Domino resolves the trade-o between performance and noise margins in conventional CD-Domino logic while dissipat...
Mohamed W. Allam, Mohab Anis, Mohamed I. Elmasry
GLVLSI
2006
IEEE
145views VLSI» more  GLVLSI 2006»
13 years 11 months ago
Leakage current starved domino logic
A new circuit technique based on a single PMOS sleep transistor and a dual threshold voltage CMOS technology is proposed in this paper for simultaneously reducing subthreshold and...
Zhiyu Liu, Volkan Kursun
GLVLSI
2003
IEEE
152views VLSI» more  GLVLSI 2003»
13 years 10 months ago
Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs
The realization of fast datapaths in signal processing environments requires fastest, power efficient logic styles with synchronous behavior. This paper presents a method to combi...
Frank Grassert, Dirk Timmermann