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» A Low-Speed BIST Framework for High-Performance Circuit Test...
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IOLTS
2000
IEEE
105views Hardware» more  IOLTS 2000»
13 years 9 months ago
Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. A...
Patrick Girard, Christian Landrault, Serge Pravoss...
ET
2002
84views more  ET 2002»
13 years 5 months ago
Hardware Generation of Random Single Input Change Test Sequences
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. A...
René David, Patrick Girard, Christian Landr...
ITC
1997
IEEE
80views Hardware» more  ITC 1997»
13 years 9 months ago
Scan Synthesis for One-Hot Signals
Tri-state buses and pass transistor logic are used in many complex applications to achieve high performance and small area. Such circuits often contain logic requiring one-hot sig...
Subhasish Mitra, LaNae J. Avra, Edward J. McCluske...