Sciweavers

Share
ET
2002

Hardware Generation of Random Single Input Change Test Sequences

8 years 11 months ago
Hardware Generation of Random Single Input Change Test Sequences
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. As delay testing using external testers requires expensive ATE, built-in self test (BIST) is an alternative technique that can significantly reduce the test cost. It has been proven that Single Input Change (SIC) test sequences are more effective than classical Multiple Input Change (MIC) test sequences when a high robust delay fault coverage is targeted. It has also been shown that random SIC (RSIC) test sequences achieve a higher fault coverage than random MIC (RMIC) test sequences when both robust and non robust tests are under consideration; the experimental results were based on a software generation of RSIC sequences that are easily generated. Obviously, a hardware RSIC generation providing similar results can be obtained. However, this hardware generator must be carefully designed. In this paper, it is ...
René David, Patrick Girard, Christian Landr
Added 18 Dec 2010
Updated 18 Dec 2010
Type Journal
Year 2002
Where ET
Authors René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
Comments (0)
books