22 search results - page 1 / 5 » A New Functional Fault Model for FPGA Application-Oriented T... |
DFT
2002
IEEE
13 years 10 months ago
2002
IEEE
1 The objective of this paper is to propose a new fault model suitable for test pattern generation for an FPGA configured to implement a given application. The paper demonstrates t...
ATS
2000
IEEE
13 years 9 months ago
2000
IEEE
: In this paper a complete analysis of spot defects in industrial SRAMs will be presented. All possible defects are simulated, and the resulting electrical faults are transformed i...
ERSA
2010
13 years 2 months ago
2010
SRAM-based FPGA devices are an attractive option for data processing on space-based platforms, due to high computational capabilities and a lower power envelope than traditional pr...
ATS
2003
IEEE
13 years 10 months ago
2003
IEEE
The analysis of linked faults has proven to be a source for new memory tests, characterized by an increased fault coverage. The paper gives a set of five new tests to target all ...
GLVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
The path-delay fault simulation of functional tests on complex circuits such as current processor-based systems is a daunting task. The amount of computing power and memory needed...