45 search results - page 2 / 9 » A New System Design Methodology for Wire Pipelined SoC |
IPPS
2006
IEEE
13 years 11 months ago
2006
IEEE
Modern FPGA platforms provide the hardware and software infrastructure for building a bus-based System on Chip (SoC) that meet the applications requirements. The designer can cust...
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the...
DAC
2006
ACM
14 years 6 months ago
2006
ACM
Modern integrated circuits (ICs) are becoming increasingly complex. The complexity makes it difficult to design, manufacture and integrate these high-performance ICs. The advent o...
ISCAS
2005
IEEE
13 years 11 months ago
2005
IEEE
— As across-chip wire delays exceed a clock cycle, interconnect pipelining becomes essential. However, the arbitrary insertion of flip-flops can change the differentials of lat...
DAC
2007
ACM
14 years 6 months ago
2007
ACM
Multiprocessor SoC systems have led to the increasing use of parallel hardware along with the associated software. These approaches have included coprocessor, homogeneous processo...