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» A Novel Parity Bit Scheme for SBox in AES Circuits
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DDECS
2007
IEEE
121views Hardware» more  DDECS 2007»
13 years 11 months ago
A Novel Parity Bit Scheme for SBox in AES Circuits
– This paper addresses an efficient concurrent fault detection scheme for the SBox hardware implementation of the AES algorithm. Concurrent fault detection is important not only ...
Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouze...
ISQED
2010
IEEE
156views Hardware» more  ISQED 2010»
13 years 7 months ago
On the design of different concurrent EDC schemes for S-Box and GF(p)
Recent studies have shown that an attacker can retrieve confidential information from cryptographic hardware (e.g. the secret key) by introducing internal faults. A secure and re...
Jimson Mathew, Hafizur Rahaman, Abusaleh M. Jabir,...
DFT
2007
IEEE
101views VLSI» more  DFT 2007»
13 years 11 months ago
Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits
Many side-channel attacks on implementations of cryptographic algorithms have been developed in recent years demonstrating the ease of extracting the secret key. In response, vari...
Francesco Regazzoni, Thomas Eisenbarth, Johann Gro...
DFT
2008
IEEE
149views VLSI» more  DFT 2008»
13 years 7 months ago
Can Knowledge Regarding the Presence of Countermeasures Against Fault Attacks Simplify Power Attacks on Cryptographic Devices?
Side-channel attacks are nowadays a serious concern when implementing cryptographic algorithms. Powerful ways for gaining information about the secret key as well as various count...
Francesco Regazzoni, Thomas Eisenbarth, Luca Breve...
HOST
2008
IEEE
13 years 11 months ago
Slicing Up a Perfect Hardware Masking Scheme
—Masking is a side-channel countermeasure that randomizes side-channel leakage, such as the power dissipation of a circuit. Masking is only effective on the condition that the in...
Zhimin Chen, Patrick Schaumont