66 search results - page 3 / 14 » A Probabilistic Approach to Buffer Insertion |
ICCAD
2004
IEEE
14 years 2 months ago
2004
IEEE
Closed formed expressions for buffered interconnect delay approximation have been around for some time. However, previous approaches assume that buffers are free to be placed anyw...
ISCAS
2005
IEEE
13 years 11 months ago
2005
IEEE
-- Timing optimization is an important goal of global routing in deep submicron era. To guarantee the timing performance of the circuit, merely adopting topology optimization becom...
DAC
1999
ACM
13 years 9 months ago
1999
ACM
Buffer insertion has become a critical step in deep submicron design, and several buffer insertion/sizing algorithms have been proposed in the literature. However, most of these m...
ICCD
2004
IEEE
14 years 2 months ago
2004
IEEE
In this paper, we propose a combined channel segmentation and buffer insertion approach, which minimizes the number of buffers inserted while satisfying the delay constraints for ...
TCAD
2008
13 years 5 months ago
2008
Recently, the microprocessor industry is headed in the direction of multicore designs in order to continue the chip performance growth. We investigate buffer insertion, which is a ...