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ISQED
2003
IEEE
71views Hardware» more  ISQED 2003»
13 years 10 months ago
A Proposal for Routing-Based Timing-Driven Scan Chain Ordering
Scan chain insertion can have large impact on routability, wirelength and timing. We propose a routing-driven and timing-aware methodology for scan insertion with minimum wireleng...
Puneet Gupta, Andrew B. Kahng, Stefanus Mantik
ASPDAC
2006
ACM
90views Hardware» more  ASPDAC 2006»
13 years 10 months ago
A routability constrained scan chain ordering technique for test power reduction
Abstract— For scan-based testing, the high test power consumption may cause test power management problems, and the extra scan chain connections may cause routability degradation...
X.-L. Huang, J.-L. Huang
ICCD
2007
IEEE
161views Hardware» more  ICCD 2007»
14 years 1 months ago
Scan chain design for three-dimensional integrated circuits (3D ICs)
Scan chains are widely used to improve the testability of IC designs. In traditional 2D IC designs, various design techniques on the construction of scan chains have been proposed...
Xiaoxia Wu, Paul Falkenstern, Yuan Xie
DATE
2006
IEEE
109views Hardware» more  DATE 2006»
13 years 10 months ago
A secure scan design methodology
It has been proven that scan path is a potent hazard for secure chips. Scan based attacks have been recently demonstrated against DES or AES and several solutions have been presen...
David Hély, Frédéric Bancel, ...
ATS
2004
IEEE
87views Hardware» more  ATS 2004»
13 years 8 months ago
Low Power BIST with Smoother and Scan-Chain Reorder
In this paper, we propose a low-power testing methodology for the scan-based BIST. A smoother is included in the test pattern generator (TPG) to reduce average power consumption d...
Nan-Cheng Lai, Sying-Jyan Wang, Yu-Hsuan Fu