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IPPS
2006
IEEE
13 years 11 months ago
Exploiting processing locality through paging configurations in multitasked reconfigurable systems
FPGA chips in reconfigurable computer systems are used as malleable coprocessors where components of a hardware library of functions can be configured as needed. As the number of ...
T. Taher, Tarek A. El-Ghazawi
IPPS
2007
IEEE
13 years 11 months ago
A Multi-Level Parallel Implementation of a Program for Finding Frequent Patterns in a Large Sparse Graph
Graphs capture the essential elements of many problems broadly defined as searching or categorizing. With the rapid increase of data volumes from sensors, many application discipl...
Steve Reinhardt, George Karypis
ERSA
2004
134views Hardware» more  ERSA 2004»
13 years 6 months ago
A High Performance Application Representation for Reconfigurable Systems
Modern reconfigurable computing systems feature powerful hybrid architectures with multiple microprocessor cores, large reconfigurable logic arrays and distributed memory hierarch...
Wenrui Gong, Gang Wang, Ryan Kastner
IPPS
2005
IEEE
13 years 11 months ago
Analysis of Hardware Acceleration in Reconfigurable Embedded Systems
Embedded designers now have the capability of offloading software routines into custom applicationspecific hardware blocks. This paper evaluates a domain-specific design system fo...
Matthew Ouellette, Daniel A. Connors
IPPS
2007
IEEE
13 years 11 months ago
An Architectural Framework for Automated Streaming Kernel Selection
Hardware accelerators are increasingly used to extend the computational capabilities of baseline scalar processors to meet the growing performance and power requirements of embedd...
Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan L...