5 search results - page 1 / 1 » A Scalable VLSI Architecture for Binary Prefix Sums |
IPPS
1998
IEEE
13 years 9 months ago
1998
IEEE
The task of computingbinary prefix sums (BPS, for short) arises, for example, in expression evaluation, data and storage compaction, and routing. This paper describes a scalable V...
IPPS
1999
IEEE
13 years 9 months ago
1999
IEEE
Abstract. Themain contributionof thiswork isto propose a numberof broadcastefficient VLSI architectures for computing the sum and the prefix sums of a w k-bit, k 2, binary sequenc...
IPPS
1999
IEEE
13 years 9 months ago
1999
IEEE
We propose an efficient reconfigurable parallel prefix counting network based on the recently-proposed technique of shift switching with domino logic, where the charge/discharge s...
FCCM
2009
IEEE
13 years 8 months ago
2009
IEEE
Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. Due to the available on-chip memory and the number of I/O pins of Field Programmab...
FCCM
2005
IEEE
13 years 10 months ago
2005
IEEE
Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously in...