20 search results - page 1 / 4 » A Survey of Optimization Techniques Targeting Low Power VLSI... |
DAC
1995
ACM
13 years 8 months ago
1995
ACM
—We survey state-of-the-art optimization methods that target low power dissipation in VLSI circuits. Optimizations at the circuit, logic, architectural and system levels are cons...
ICCAD
1995
IEEE
13 years 8 months ago
1995
IEEE
ISQED
2000
IEEE
13 years 9 months ago
2000
IEEE
Power and energy consumption of digital systems may increase significantly during testing. This extra power consumption due to test application may give rise to severe hazards to ...
ISLPED
1999
ACM
13 years 9 months ago
1999
ACM
The use of dual threshold voltages can significantly reduce the static power dissipated in CMOS VLSI circuits. With the supply voltage at 1V and threshold voltage as low as 0.2V ...
ISVLSI
2002
IEEE
13 years 9 months ago
2002
IEEE
Timed Shannon circuits have been proposed as a synthesis approach for a low power optimization technique at the logic level since overall circuit switching probabilities may be re...