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» A Survey of Optimization Techniques Targeting Low Power VLSI...
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DAC
2004
ACM
14 years 6 months ago
FPGA power reduction using configurable dual-Vdd
Power optimization is of growing importance for FPGAs in nanometer technologies. Considering dual-Vdd technique, we show that configurable power supply is required to obtain a sat...
Fei Li, Yan Lin, Lei He
GLVLSI
2009
IEEE
143views VLSI» more  GLVLSI 2009»
13 years 9 months ago
Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO
In this paper, we present the design of a P4 (Power-PerformanceProcess-Parasitic) aware voltage controlled oscillator (VCO) at nanoCMOS technologies. Through simulations, we have ...
Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos
FTEDA
2008
75views more  FTEDA 2008»
13 years 5 months ago
Thermally Aware Design
With greater integration, the power dissipation in integrated circuits has begun to outpace the ability of today's heat sinks to limit the on-chip temperature. As a result, t...
Yong Zhan, Sanjay V. Kumar, Sachin S. Sapatnekar
GLVLSI
2005
IEEE
124views VLSI» more  GLVLSI 2005»
13 years 11 months ago
A first look at the interplay of code reordering and configurable caches
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
ISCAS
2008
IEEE
125views Hardware» more  ISCAS 2008»
13 years 11 months ago
Ultra-low-power UWB for sensor network applications
— Long distance, low data-rate UWB communication for sensor network applications requires a highly energy efficient transceiver combined with circuit and system-level optimizati...
Patrick P. Mercier, Denis C. Daly, Manish Bhardwaj...