Sciweavers

28 search results - page 1 / 6
» A Unified Approach for SOC Testing Using Test Data Compressi...
Sort
View
DATE
2003
IEEE
76views Hardware» more  DATE 2003»
13 years 10 months ago
A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization
Vikram Iyengar, Anshuman Chandra, Sharon Schweizer...
DATE
2007
IEEE
100views Hardware» more  DATE 2007»
13 years 11 months ago
SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling
Abstract— We present an SoC testing approach that integrates test data compression, TAM/test wrapper design, and test scheduling. An improved LFSR reseeding technique is used as ...
Zhanglei Wang, Krishnendu Chakrabarty, Seongmoon W...
VTS
2002
IEEE
126views Hardware» more  VTS 2002»
13 years 9 months ago
On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization
The testing time for a system-on-chip (SOC) is determined to a large extent by the design of test wrappers and the test access mechanism (TAM). Wrapper/TAM co-optimization is ther...
Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan M...
ICCAD
2003
IEEE
105views Hardware» more  ICCAD 2003»
14 years 1 months ago
TAM Optimization for Mixed-Signal SOCs using Analog Test Wrappers
We present a new approach for TAM optimization and test scheduling in the modular testing of mixed-signal SOCs. A test planning approach for digital SOCs is extended to handle ana...
Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty
ET
2002
90views more  ET 2002»
13 years 4 months ago
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrappe...
Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan M...