Abstract— We present an SoC testing approach that integrates test data compression, TAM/test wrapper design, and test scheduling. An improved LFSR reseeding technique is used as ...
The testing time for a system-on-chip (SOC) is determined to a large extent by the design of test wrappers and the test access mechanism (TAM). Wrapper/TAM co-optimization is ther...
Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan M...
We present a new approach for TAM optimization and test scheduling in the modular testing of mixed-signal SOCs. A test planning approach for digital SOCs is extended to handle ana...
Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrappe...
Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan M...