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» A VLSI Algorithm for Modular Multiplication Division
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ARITH
2003
IEEE
13 years 10 months ago
A VLSI Algorithm for Modular Multiplication/Division
We propose an algorithm for modular multiplication/division suitable for VLSI implementation. The algorithm is based on Montgomery’s method for modular multiplication and on the...
Marcelo E. Kaihara, Naofumi Takagi
ARITH
2007
IEEE
13 years 11 months ago
Modular Multiplication using Redundant Digit Division
Most implementations of the modular exponentiation, ME mod N, computation in cryptographic algorithms employ Montgomery multiplication, ABR−1 mod N, instead of modular multiplic...
Ping Tak Peter Tang
CHES
2003
Springer
119views Cryptology» more  CHES 2003»
13 years 10 months ago
Faster Double-Size Modular Multiplication from Euclidean Multipliers
Abstract. A novel technique for computing a 2n-bit modular multiplication using n-bit arithmetic was introduced at CHES 2002 by Fischer and Seifert. Their technique makes use of an...
Benoît Chevallier-Mames, Marc Joye, Pascal P...
GLVLSI
2007
IEEE
166views VLSI» more  GLVLSI 2007»
13 years 8 months ago
Efficient pipelining for modular multiplication architectures in prime fields
This paper presents a pipelined architecture of a modular Montgomery multiplier, which is suitable to be used in public key coprocessors. Starting from a baseline implementation o...
Nele Mentens, Kazuo Sakiyama, Bart Preneel, Ingrid...
VLSISP
2002
98views more  VLSISP 2002»
13 years 4 months ago
VLSI Implementation of the Multistage Detector for Next Generation Wideband CDMA Receivers
The multistage detection algorithm has been proposed as an effective interference cancellation scheme for next generation Wideband Code Division Multiple Access (W-CDMA) base stati...
Gang Xu, Sridhar Rajagopal, Joseph R. Cavallaro, B...