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CF
2006
ACM
13 years 8 months ago
An efficient cache design for scalable glueless shared-memory multiprocessors
Traditionally, cache coherence in large-scale shared-memory multiprocessors has been ensured by means of a distributed directory structure stored in main memory. In this way, the ...
Alberto Ros, Manuel E. Acacio, José M. Garc...
CASES
2000
ACM
13 years 9 months ago
PROMPT: a mapping environment for telecom applications on "system-on-a-chip"
Increasing of computation needs and improving of processor integration make the mapping of embedded real-time applications more and more expensive. PROMPT [1] provides a new appro...
Michel Barreteau, Juliette Mattioli, Thierry Grand...
CASES
2006
ACM
13 years 11 months ago
Integrated scratchpad memory optimization and task scheduling for MPSoC architectures
Multiprocessor system-on-chip (MPSoC) is an integrated circuit containing multiple instruction-set processors on a single chip that implements most of the functionality of a compl...
Vivy Suhendra, Chandrashekar Raghavan, Tulika Mitr...
ISCA
1994
IEEE
104views Hardware» more  ISCA 1994»
13 years 9 months ago
Exploring the Design Space for a Shared-Cache Multiprocessor
In the near future, semiconductor technology will allow the integration of multiple processors on a chip or multichipmodule (MCM). In this paper we investigate the architecture an...
Basem A. Nayfeh, Kunle Olukotun
CIDR
2007
173views Algorithms» more  CIDR 2007»
13 years 6 months ago
Database Servers on Chip Multiprocessors: Limitations and Opportunities
Prior research shows that database system performance is dominated by off-chip data stalls, resulting in a concerted effort to bring data into on-chip caches. At the same time, hi...
Nikos Hardavellas, Ippokratis Pandis, Ryan Johnson...