11 search results - page 1 / 3 » A codesigned on-chip logic minimizer |
FCCM
2005
IEEE
13 years 10 months ago
2005
IEEE
Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously in...
DSD
2007
IEEE
13 years 8 months ago
2007
IEEE
In this study, we investigate different cache fault tolerance techniques to determine which will be most effective when on-chip memory cell defect probabilities exceed those of cu...
DAC
2007
ACM
14 years 5 months ago
2007
ACM
This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
ASAP
2004
IEEE
13 years 8 months ago
2004
IEEE
Large register file with multiple ports is a critical component of a high-performance processor. A large number of registers are necessary for processing a larger number of in-fli...
DAC
2005
ACM
13 years 6 months ago
2005
ACM
This paper presents an eļ¬cient hardware architecture of an on-chip logic minimization coprocessor. The proposed architecture employs TCAM cells to provide fastest and memory eļ¬...