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GECCO
2009
Springer
108views Optimization» more  GECCO 2009»
13 years 9 months ago
Development of combinational circuits using non-uniform cellular automata: initial results
A non-uniform cellular automata-based model is presented for the evolutionary development of digital circuits at the gate level. The main feature of this model is the modified lo...
Michal Bidlo, Zdenek Vasícek
DAC
2007
ACM
14 years 5 months ago
Enhancing FPGA Performance for Arithmetic Circuits
FPGAs offer flexibility and cost-effectiveness that ASICs cannot match; however, their performance is quite poor in comparison, especially for arithmetic dominated circuits. To ad...
Philip Brisk, Ajay K. Verma, Paolo Ienne, Hadi Par...
GECCO
2004
Springer
182views Optimization» more  GECCO 2004»
13 years 10 months ago
On the Evolution of Analog Electronic Circuits Using Building Blocks on a CMOS FPTA
This article summarizes two experiments utilizing building blocks to find analog electronic circuits on a CMOS Field Programmable Transistor Array (FPTA). The FPTA features 256 pr...
Jörg Langeheine, Martin Trefzer, Daniel Br&uu...
MICRO
2002
IEEE
131views Hardware» more  MICRO 2002»
13 years 4 months ago
Protocol Wrappers for Layered Network Packet Processing in Reconfigurable Hardware
abstracting the operation of lower-level packet processing functions. The library synthesizes into field-programmable gate array (FPGA) logic and is utilized in a network platform ...
Florian Braun, John W. Lockwood, Marcel Waldvogel
AHS
2007
IEEE
231views Hardware» more  AHS 2007»
13 years 11 months ago
Debug Support for Hybrid SoCs
System-on-Chip devices containing both conventional and reconfigurable circuits are increasing in popularity. However the on-chip debug support infrastructure required to aid syst...
Andrew B. T. Hopkins, Klaus D. McDonald-Maier