Sciweavers

34 search results - page 4 / 7
» A compiler framework for mapping applications to a coarse-gr...
Sort
View
ISCAS
2005
IEEE
125views Hardware» more  ISCAS 2005»
13 years 11 months ago
A methodology for partitioning DSP applications in hybrid reconfigurable systems
—In this paper, we describe an automated and formalized methodology for partitioning computational intensive applications between reconfigurable hardware blocks of different gran...
Michalis D. Galanis, Athanasios Milidonis, George ...
CDES
2006
184views Hardware» more  CDES 2006»
13 years 7 months ago
Compilation for Future Nanocomputer Architectures
Compilation has a long history of translating a programmer's human-readable code into machine instructions designed to make good use of a specific target computer. In this pa...
Thomas P. Way
DATE
2004
IEEE
107views Hardware» more  DATE 2004»
13 years 9 months ago
A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms
In this paper, we propose a methodology for partitioning and mapping computational intensive applications in reconfigurable hardware blocks of different granularity. A generic hyb...
Michalis D. Galanis, Athanasios Milidonis, George ...
IPPS
2007
IEEE
14 years 2 days ago
An Architectural Framework for Automated Streaming Kernel Selection
Hardware accelerators are increasingly used to extend the computational capabilities of baseline scalar processors to meet the growing performance and power requirements of embedd...
Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan L...
DAC
2000
ACM
14 years 6 months ago
Hardware-software co-design of embedded reconfigurable architectures
In this paper we describe a new hardware/software partitioning approach for embedded reconfigurable architectures consisting of a general-purpose processor (CPU), a dynamically re...
Yanbing Li, Tim Callahan, Ervan Darnell, Randolph ...