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IPPS
2006
IEEE
13 years 11 months ago
A configuration memory hierarchy for fast reconfiguration with reduced energy consumption overhead
Currently run-time reconfigurable hardware offers really attractive features for embedded systems, such as flexibility, reusability, high performance and, in some cases, low-power...
Elena Perez Ramo, Javier Resano, Daniel Mozos, Fra...
DAC
2009
ACM
14 years 6 months ago
A DVS-based pipelined reconfigurable instruction memory
Energy consumption is of significant concern in battery operated embedded systems. In the processors of such systems, the instruction cache consumes a significant fraction of the ...
Zhiguo Ge, Tulika Mitra, Weng-Fai Wong
DAC
2007
ACM
14 years 6 months ago
A Self-Tuning Configurable Cache
The memory hierarchy of a system can consume up to 50% of microprocessor system power. Previous work has shown that tuning a configurable cache to a particular application can red...
Ann Gordon-Ross, Frank Vahid
MICRO
2000
IEEE
121views Hardware» more  MICRO 2000»
13 years 8 months ago
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
Conventional microarchitectures choose a single memory hierarchy design point targeted at the average application. In this paper, we propose a cache and TLB layout and design that...
Rajeev Balasubramonian, David H. Albonesi, Alper B...
ISLPED
2005
ACM
150views Hardware» more  ISLPED 2005»
13 years 10 months ago
Fast configurable-cache tuning with a unified second-level cache
Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...
Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt