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    GLVLSI
    2006
    IEEE
    112views VLSI» more  GLVLSI 2006»
    A design methodology for temperature variation insensitive low power circuits
    13 years 10 months ago
    A design methodology for temperature variation insensitive low power circuits
    Download  ihome.ust.hk
    Operating an integrated circuit at the prescribed nominal supply voltage is not preferable for reliable circuit operation under temperature fluctuations. A design methodology base...
    Ranjith Kumar, Volkan Kursun
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    DAC
    2007
    ACM
    131views Computer Architecture» more  DAC 2007»
    Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
    14 years 5 months ago
    Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop
    Download  cobweb.ecn.purdue.edu
    This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
    Kunhyuk Kang, Kee-Jong Kim, Kaushik Roy
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    ASPDAC
    2011
    ACM
    167views Hardware» more  ASPDAC 2011»
    Variation-tolerant and self-repair design methodology for low temperature polycrystalline silicon liquid crystal and organic lig
    12 years 8 months ago
    Variation-tolerant and self-repair design methodology for low temperature polycrystalline silicon liquid crystal and organic lig
    Download  web.ics.purdue.edu
    - In low temperature polycrystalline silicon (LTPS) based display technologies, the electrical parameter variations in thin film transistors (TFTs) caused by random grain boundarie...
    Chih-Hsiang Ho, Chao Lu, Debabrata Mohapatra, Kaus...
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    TVLSI
    2008
    99views more  TVLSI 2008»
    A Design-Specific and Thermally-Aware Methodology for Trading-Off Power and Performance in Leakage-Dominant CMOS Technologies
    13 years 4 months ago
    A Design-Specific and Thermally-Aware Methodology for Trading-Off Power and Performance in Leakage-Dominant CMOS Technologies
    Download  www.ece.ucsb.edu
    As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for high-performance VLSI des...
    Sheng-Chih Lin, Kaustav Banerjee
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    ASPDAC
    2008
    ACM
    104views Hardware» more  ASPDAC 2008»
    Low power clock buffer planning methodology in F-D placement for large scale circuit design
    13 years 6 months ago
    Low power clock buffer planning methodology in F-D placement for large scale circuit design
    Download  dropzone.tamu.edu
    Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
    Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xian...
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