31 search results - page 5 / 7 » A fusion-based approach for tolerating faults in finite stat... |
DFT
2007
IEEE
14 years 3 days ago
2007
IEEE
The paper discusses a novel approach for reduction of fault detection latency in a selfchecking sequential circuit. The Authors propose decomposing the finite state machine (FSM) ...
ATS
2003
IEEE
13 years 11 months ago
2003
IEEE
Software-based self-testing is a promising approach for the testing of processor cores which are embedded inside a System-on-a-Chip (SoC), as it can apply test vectors in function...
PADS
2006
ACM
13 years 11 months ago
2006
ACM
A master/worker paradigm for executing large-scale parallel discrete event simulation programs over networkenabled computational resources is proposed and evaluated. In contrast t...
VTS
1998
IEEE
13 years 10 months ago
1998
IEEE
This paper presents a BIST architecture for Finite State Machines that exploits Cellular Automata (CA) as pattern generators and signature analyzers. The main advantage of the pro...
CSREAESA
2008
13 years 7 months ago
2008
A group testing-based BIST technique to identify faulty hard cores in FPGA devices is presented. The method provides for isolation of faults in embedded cores as demonstrated by ex...