105 search results - page 2 / 21 » A gate resizing technique for high reduction in power consum... |
ASPDAC
1995
ACM
13 years 8 months ago
1995
ACM
— The goal of transistor reordering for a logic gate is to reduce the propagation delay as well as the charging and discharging of internal capacitances to achieve low power cons...
FPL
2009
Springer
13 years 9 months ago
2009
Springer
Motion Estimation (ME) is the most computationally intensive and the most power consuming part of video compression and video enhancement systems. In this paper, we propose a nove...
DATE
2010
IEEE
13 years 10 months ago
2010
IEEE
Ambipolar devices have been reported in many technologies, including carbon nanotube field effect transistors (CNTFETs). The ambipolarity can be in-field controlled with a secon...
ISCAS
2005
IEEE
13 years 10 months ago
2005
IEEE
—Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits is presented in this paper. Noise immunity is enhanced by conditionally turning on the conditional k...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
— This paper suggests a methodology to decrease the power of a static CMOS standard cell design at layout level by focusing on switched capacitance. The term switched is the key:...