74 search results - page 2 / 15 » A low power approach to system level pipelined interconnect ... |
HOTI
2008
IEEE
14 years 6 days ago
2008
IEEE
Several types of low power passive equalizer is proposed and optimized in this work. The equalizer topologies include T-junction, parallel R-C and series R-L structures. These str...
DSD
2007
IEEE
14 years 3 days ago
2007
IEEE
Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the ...
HPCA
2005
IEEE
13 years 11 months ago
2005
IEEE
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
ICCAD
2002
IEEE
14 years 2 months ago
2002
IEEE
Approaches to achieve low-power and high-speed VLSI's are described with the emphasis on techniques across multiple technology and design levels. To suppress the leakage curr...
GLVLSI
2003
IEEE
13 years 11 months ago
2003
IEEE
The realization of fast datapaths in signal processing environments requires fastest, power efficient logic styles with synchronous behavior. This paper presents a method to combi...