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GLVLSI
2003
IEEE
119views VLSI» more  GLVLSI 2003»
13 years 10 months ago
Simultaneous peak and average power minimization during datapath scheduling for DSP processors
The use of multiple supply voltages for energy and average power reduction is well researched and several works have appeared in the literature. However, in low power design using...
Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappi...
LCPC
2004
Springer
13 years 10 months ago
Power-Aware Scheduling for Parallel Security Processors with Analytical Models
Techniques to reduce power dissipation for embedded systems have recently come into sharp focus in the technology development. Among these techniques, dynamic voltage scaling (DVS)...
Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq ...
VLSID
2003
IEEE
92views VLSI» more  VLSID 2003»
14 years 5 months ago
Energy Efficient Scheduling for Datapath Synthesis
In this paper, we describe two new algorithms for datapath scheduling which aim at energy reduction while maintaining performance. The proposed algorithms, time constrained and re...
Saraju P. Mohanty, N. Ranganathan
ASPDAC
2005
ACM
109views Hardware» more  ASPDAC 2005»
13 years 10 months ago
Optimal module and voltage assignment for low-power
– Reducing power consumption through high-level synthesis has attracted a growing interest from researchers due to its large potential for power reduction. In this work we study ...
Deming Chen, Jason Cong, Junjuan Xu
ISCAS
2005
IEEE
144views Hardware» more  ISCAS 2005»
13 years 10 months ago
Impact of multicycled scheduling on power-area tradeoffs in behavioural synthesis
— Multicycling is a widely investigated technique for performance optimisation in behavioural synthesis. It allows an operation to execute over two or more control steps with the...
M. A. Ochoa-Montiel, Bashir M. Al-Hashimi, Peter K...