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» A low power switching power supply for self-clocked systems
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CDES
2006
240views Hardware» more  CDES 2006»
13 years 6 months ago
Design of Low Power 4-Tap 8-Bit Adiabatic FIR Filter
Abstract-- Digital signal processing (DSP) is used to perform filtering, decimation and down conversion in common communications systems, like in oversampling analog to digital con...
Arun N. Chandorkar, Gurvinder Singh
ICCD
2008
IEEE
111views Hardware» more  ICCD 2008»
14 years 1 months ago
Power switch characterization for fine-grained dynamic voltage scaling
—Dynamic voltage scaling (DVS) provides power savings for systems with varying performance requirements. One low overhead implementation of DVS uses PMOS power switches to connec...
Liang Di, Mateja Putic, John Lach, Benton H. Calho...
HIPEAC
2009
Springer
13 years 11 months ago
Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture
In this article, we present a parallel implementation of a 1024 point Fast Fourier Transform (FFT) operating with a subthreshold supply voltage, which is below the voltage that tur...
Michael B. Henry, Leyla Nazhandali
ICCAD
1995
IEEE
135views Hardware» more  ICCAD 1995»
13 years 8 months ago
An iterative improvement algorithm for low power data path synthesis
We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects ...
Anand Raghunathan, Niraj K. Jha
ISCAS
2007
IEEE
123views Hardware» more  ISCAS 2007»
13 years 11 months ago
Low-Power Low-Voltage Hot-Spot Tolerant Clocking with Suppressed Skew
— A methodology based on supply voltage optimization for lowering the power consumption and temperature fluctuations induced skew of clock distribution networks is proposed in th...
Sherif A. Tawfik, Volkan Kursun