Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture

In this article, we present a parallel implementation of a 1024 point Fast Fourier Transform (FFT) operating with a subthreshold supply voltage, which is below the voltage that turns the transistors on and off. Even though the transistors are not actually switching as usual in this region, they are able to complete the computation by modulating the leakage current that passes through them, resulting in a 20-100x decrease in power consumption. Our hybrid FFT design partitions a sequential butterfly FFT architecture into two regions, namely memory banks and processing elements, such that the former runs in the superthreshold region and the latter in the subthreshold region. For a given throughput, the number of parallel processing units and their supply voltage is determined such that the overall power consumption of the design is minimized. For a 1024 point FFT operation, our parallel design is able to deliver the same throughput as a serial design, while consuming 70% less power. We ...

• Type: Conference
• Year: 2009
• Where: HIPEAC
• Authors: Michael B. Henry, Leyla Nazhandali
• Keywords: HIPEAC 2009, Power Consumption, Supply Voltage, System Software, Throughput