10 search results - page 1 / 2 » A low spur fractional-N frequency synthesizer architecture |
ISQED
2010
IEEE
13 years 6 months ago
2010
IEEE
Digital implementation of analog function is becoming attractive in CMOS ICs, given the low supply voltage of ultra-scaled process. The conventional fractional-N frequency synthes...
ISCAS
2005
IEEE
13 years 10 months ago
2005
IEEE
— A new architecture of a fractional-N phase-locked loop (PLL) frequency synthesizer is presented in this paper. The unique feature of the proposed frequency synthesizer is a loo...
ISCAS
2007
IEEE
13 years 11 months ago
2007
IEEE
−In this paper, a novel architecture of a fractional-N phase-locked loop (PLL) is presented for digital clock generation. By employing multimodulus dividers in parallel with sequ...
ISCAS
2007
IEEE
13 years 11 months ago
2007
IEEE
— Diophantine Frequency Synthesis1 is a new approach to fine-step and fast-hopping frequency synthesis that is based on mathematical properties of integer numbers and Diophantin...
GLVLSI
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper presents a fully integrated 1-V, dual band, fastlocked frequency synthesizer for IEEE 802.11 a/b/g WLAN applications. It can synthesize frequencies in the range of 2.4 ...