45 search results - page 2 / 9 » A low-SER efficient core processor architecture for future t... |
ISCAS
2008
IEEE
13 years 11 months ago
2008
IEEE
—Software-based self-test (SBST) is a promising new technology for at-speed testing of embedded processors in SoC systems. This paper introduces an effective and efficient new ho...
ERSA
2010
13 years 2 months ago
2010
Interconnect architecture is a primary research issue for emerging many-core processors. Packet switched Networks-on-Chip (NoCs) are considered key to success but since they delive...
SIGARCH
2008
13 years 4 months ago
2008
While technology trends have ushered in the age of chip multiprocessors (CMP) and enabled designers to place an increasing number of cores on chip, a fundamental question is what ...
VLSISP
2008
13 years 4 months ago
2008
Abstract-- This paper presents the architecture of an Asynchronous Array of simple Processors (AsAP), and evaluates its key architectural features as well as its performance and en...
CASES
2006
ACM
13 years 8 months ago
2006
ACM
Technology scaling trends have forced designers to consider alternatives to deeply pipelining aggressive cores with large amounts of performance accelerating hardware. One alterna...