45 search results - page 3 / 9 » A low-SER efficient core processor architecture for future t... |
MICRO
2010
IEEE
13 years 2 months ago
2010
IEEE
Single-thread performance, reliability and power efficiency are critical design challenges of future multicore systems. Although point solutions have been proposed to address thes...
PPL
2008
13 years 4 months ago
2008
As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either ...
ISCA
1999
IEEE
13 years 9 months ago
1999
IEEE
In the pursuit of instruction-level parallelism, significant demands are placed on a processor's instruction delivery mechanism. Delivering the performance necessary to meet ...
DAC
2005
ACM
14 years 5 months ago
2005
ACM
Channel estimation and multiuser detection are enabling technologies for future generations of wireless applications. However, sophisticated algorithms are required for accurate c...
ASPLOS
2006
ACM
13 years 8 months ago
2006
ACM
Transient faults are expected a be a major design consideration in future microprocessors. Recent proposals for transient fault detection in processor cores have revolved around t...