6 search results - page 1 / 2 » A low-cost concurrent error detection technique for processo... |
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
This paper presents a concurrent error detection technique targeted towards control logic in a processor with emphasis on low area overhead. Rather than detect all modeled transie...
DFT
2008
IEEE
13 years 6 months ago
2008
IEEE
This paper presents a concurrent error detection technique for the control logic of a modern microprocessor. Our method is based on execution time prediction for each instruction ...
FTCS
1994
13 years 6 months ago
1994
This paper examines architectural techniques for providing concurrent error detection in self-timed VLSI pipelines. Signal pairs from Differential Cascode Voltage Switch Logic are...
EDCC
2006
Springer
13 years 8 months ago
2006
Springer
The importance of fault tolerance at the processor architecture level has been made increasingly important due to rapid advancements in the design and usage of high performance de...
DFT
2006
IEEE
13 years 11 months ago
2006
IEEE
Control flow checking (CFC) is a well known concurrent checking technique for ensuring that a program’s instruction execution sequence follows permissible paths. Almost all CFC...