Sciweavers

3 search results - page 1 / 1
» A multilevel analytical placement for 3D ICs
Sort
View
ASPDAC
2009
ACM
145views Hardware» more  ASPDAC 2009»
13 years 11 months ago
A multilevel analytical placement for 3D ICs
Jason Cong, Guojie Luo
DAC
2007
ACM
14 years 5 months ago
Placement of 3D ICs with Thermal and Interlayer Via Considerations
Thermal problems and limitations on interlayer via densities are important design constraints on three-dimensional integrated circuits (3D ICs), and need to be considered during g...
Brent Goplen, Sachin S. Sapatnekar
ASPDAC
2005
ACM
134views Hardware» more  ASPDAC 2005»
13 years 10 months ago
Wire congestion and thermal aware 3D global placement
— The recent popularity of 3D IC technology stems from its enhanced performance capabilities and reduced wirelength. However, wire congestion and thermal issues are exacerbated d...
Karthik Balakrishnan, Vidit Nanda, Siddharth Easwa...