Sciweavers

12 search results - page 2 / 3
» A new algorithm for simultaneous gate sizing and threshold v...
Sort
View
DAC
2005
ACM
13 years 6 months ago
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages
Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt’s are common ways to meet power and timing budgets. ...
Feng Gao, John P. Hayes
DAC
2009
ACM
13 years 9 months ago
GPU-based parallelization for fast circuit optimization
The progress of GPU (Graphics Processing Unit) technology opens a new avenue for boosting computing power. This work is an attempt to exploit GPU for accelerating VLSI circuit opt...
Yifang Liu, Jiang Hu
ICCAD
2009
IEEE
161views Hardware» more  ICCAD 2009»
13 years 2 months ago
The epsilon-approximation to discrete VT assignment for leakage power minimization
As VLSI technology reaches 45nm technology node, leakage power optimization has become a major design challenge. Threshold voltage (vt) assignment has been extensively studied, du...
Yujia Feng, Shiyan Hu
ICCAD
2006
IEEE
103views Hardware» more  ICCAD 2006»
14 years 1 months ago
A statistical framework for post-silicon tuning through body bias clustering
Adaptive body biasing (ABB) is a powerful technique that allows post-silicon tuning of individual manufactured dies such that each die optimally meets the delay and power constrai...
Sarvesh H. Kulkarni, Dennis Sylvester, David Blaau...
DAC
2005
ACM
14 years 5 months ago
An efficient algorithm for statistical minimization of total power under timing yield constraints
Power minimization under variability is formulated as a rigorous statistical robust optimization program with a guarantee of power and timing yields. Both power and timing metrics...
Murari Mani, Anirudh Devgan, Michael Orshansky