26 search results - page 1 / 6 » A new congestion-driven placement algorithm based on cell in... |
ASPDAC
2001
ACM
13 years 9 months ago
2001
ACM
DATE
2010
IEEE
13 years 10 months ago
2010
IEEE
Modern FPGAs have been designed with advanced integrated circuit techniques that allow high speed and low power performance, joined to reconfiguration capabilities. This makes new...
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
− In this paper, we present a new timing-driven placement algorithm, which attempts to minimize zigzags and crisscrosses on the timing-critical paths of a circuit. We observed th...
VLSID
1996
IEEE
13 years 9 months ago
1996
IEEE
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process, and as a result several research efforts have been un...
DAC
2006
ACM
14 years 6 months ago
2006
ACM
In this paper, we propose a new linear programming based timing driven placement framework for high performance designs. Our LP framework is mainly net-based, but it takes advanta...