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TNN
2011
132views more  TNN 2011»
12 years 11 months ago
Lower Upper Bound Estimation Method for Construction of Neural Network-Based Prediction Intervals
—Prediction intervals (PIs) have been proposed in the literature to provide more information by quantifying the level of uncertainty associated to the point forecasts. Traditiona...
Abbas Khosravi, Saeid Nahavandi, Douglas C. Creigh...
VTS
2007
IEEE
135views Hardware» more  VTS 2007»
13 years 11 months ago
High Level Synthesis of Degradable ASICs Using Virtual Binding
—As the complexity of the integrated circuits increases, they become more susceptible to manufacturing faults, decreasing the total process yield. Thus, it would be desirable to ...
Nima Honarmand, A. Shahabi, Hasan Sohofi, Maghsoud...
DAC
2003
ACM
14 years 6 months ago
Data communication estimation and reduction for reconfigurable systems
Widespread adoption of reconfigurable devices requires system level synthesis techniques to take an application written in a high level language and map it to the reconfigurable d...
Adam Kaplan, Philip Brisk, Ryan Kastner
ASPDAC
1995
ACM
85views Hardware» more  ASPDAC 1995»
13 years 8 months ago
High-level synthesis scheduling and allocation using genetic algorithms
In this article a scheduling method is presented which is capable of allocating supplementary resources during scheduling. This makes it very suitable in synthesis strategies base...
Marc J. M. Heijligers, L. J. M. Cluitmans, Jochen ...
ICCAD
2002
IEEE
154views Hardware» more  ICCAD 2002»
14 years 2 months ago
Concurrent flip-flop and repeater insertion for high performance integrated circuits
For many years, CMOS process scaling has allowed a steady increase in the operating frequency and integration density of integrated circuits. Only recently, however, have we reach...
Pasquale Cocchini