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MICRO
2008
IEEE
159views Hardware» more  MICRO 2008»
13 years 11 months ago
A novel cache architecture with enhanced performance and security
—Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent f...
Zhenghong Wang, Ruby B. Lee
ACSAC
2006
IEEE
13 years 10 months ago
Covert and Side Channels Due to Processor Architecture
Information leakage through covert channels and side channels is becoming a serious problem, especially when these are enhanced by modern processor architecture features. We show ...
Zhenghong Wang, Ruby B. Lee
ICCD
2000
IEEE
107views Hardware» more  ICCD 2000»
14 years 1 months ago
Architectural Impact of Secure Socket Layer on Internet Servers
Secure socket layer SSL is the most popular protocol used in the Internet for facilitating secure communications through authentication, encryption, and decryption. Although the...
Krishna Kant, Ravishankar K. Iyer, Prasant Mohapat...
HPCA
2009
IEEE
14 years 5 months ago
Hardware-software integrated approaches to defend against software cache-based side channel attacks
Software cache-based side channel attacks present serious threats to modern computer systems. Using caches as a side channel, these attacks are able to derive secret keys used in ...
Jingfei Kong, Onur Aciiçmez, Jean-Pierre Se...
ICC
2007
IEEE
104views Communications» more  ICC 2007»
13 years 11 months ago
IPSec: Performance Analysis and Enhancements
Abstract— Internet Protocol Security (IPSec) is a widely deployed mechanism for implementing Virtual Private Networks (VPNs). In previous work, we examined the overheads incurred...
Craig A. Shue, Minaxi Gupta, Steven A. Myers