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CODES
2008
IEEE
13 years 11 months ago
Intra- and inter-processor hybrid performance modeling for MPSoC architectures
The heterogeneity of modern MPSoC architectures, coupled with the increasing complexity of the applications mapped onto them has recently led to a lot of interest in hybrid perfor...
Frank E. B. Ophelders, Samarjit Chakraborty, Henk ...
VLSID
2007
IEEE
149views VLSI» more  VLSID 2007»
14 years 5 months ago
Efficient and Accurate Statistical Timing Analysis for Non-Linear Non-Gaussian Variability With Incremental Attributes
Title of thesis: EFFICIENT AND ACCURATE STATISTICAL TIMING ANALYSIS FOR NON-LINEAR NON-GAUSSIAN VARIABILITY WITH INCREMENTAL ATTRIBUTES Ashish Dobhal, Master of Science, 2006 Thes...
Ashish Dobhal, Vishal Khandelwal, Ankur Srivastava
PPOPP
2006
ACM
13 years 11 months ago
A case study in top-down performance estimation for a large-scale parallel application
This work presents a general methodology for estimating the performance of an HPC workload when running on a future hardware architecture. Further, it demonstrates the methodology...
Ilya Sharapov, Robert Kroeger, Guy Delamarter, Raz...
HPCA
2009
IEEE
14 years 5 months ago
Accurate microarchitecture-level fault modeling for studying hardware faults
Decreasing hardware reliability is expected to impede the exploitation of increasing integration projected by Moore's Law. There is much ongoing research on efficient fault t...
Man-Lap Li, Pradeep Ramachandran, Ulya R. Karpuzcu...
SIGARCH
2008
73views more  SIGARCH 2008»
13 years 5 months ago
Servo: a programming model for many-core computing
Conventional programming models were designed to be used by expert programmers for programming for largescale multiprocessors, distributed computational clusters, or specialized p...
Nicolas Zea, John Sartori, Rakesh Kumar