30 search results - page 1 / 6 » A performance evaluator for parameterized ASIC architectures |
EURODAC
1994
IEEE
13 years 8 months ago
1994
IEEE
System-levelpartitioning assigns functionalobjects such as tasks or code segments to system-level components such as o-the-shelf processors or application-speci c architectures in...
ISCAS
2003
IEEE
13 years 10 months ago
2003
IEEE
Conventional ASIC designs are hard to be customized. Therefore DSP core-based ASIC design has potentially large payoff. This approach not only supports improved performance but al...
ISCAS
2008
IEEE
13 years 11 months ago
2008
IEEE
— In the present paper, we introduce high-performance hardware architectures for the 128-bit block cipher CLEFIA and evaluate their ASIC performances in comparison with the ISO/I...
DAC
2012
ACM
11 years 7 months ago
2012
ACM
In this paper we introduce Chisel, a new hardware construction language that supports advanced hardware design using highly parameterized generators and layered domain-specific h...
VLSID
2001
IEEE
14 years 5 months ago
2001
IEEE
The emergence of several communication architectures for System-on-Chips provides designers with a variety of design alternatives. In addition, the need to customize the system ar...