49 search results - page 3 / 10 » A power estimation methodology for systemC transaction level... |
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the...
VLSID
2005
IEEE
14 years 5 months ago
2005
IEEE
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
TCAD
2008
13 years 5 months ago
2008
We propose a methodology for the early estimation of communication implementation choices eftarting from an abstract transaction level system model (TLM). The reference version of ...
ICCD
2006
IEEE
14 years 2 months ago
2006
IEEE
— The latest development of hardware design and ation methodologies shows a trend towards abstraction levels higher than RTL, referred to as transaction level (TL). Transaction l...
ISQED
2007
IEEE
13 years 11 months ago
2007
IEEE
We propose a methodology and power models for an accurate high-level power estimation of physically partitioned and power-gated SRAM arrays. The models offer accurate estimation o...