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DATE
2009
IEEE
90views Hardware» more  DATE 2009»
13 years 11 months ago
A scalable method for the generation of small test sets
This paper presents a scalable method to generate close to minimal size test pattern sets for stuck-at faults in scan based circuits. The method creates sets of potentially compat...
Santiago Remersaro, Janusz Rajski, Sudhakar M. Red...
ET
1998
52views more  ET 1998»
13 years 4 months ago
Scalable Test Generators for High-Speed Datapath Circuits
This paper explores the design of efficient test sets and test-pattern generators for online BIST. The target applications are high-performance, scalable datapath circuits for whi...
Hussain Al-Asaad, John P. Hayes, Brian T. Murray
QSIC
2003
IEEE
13 years 10 months ago
Generating Small Combinatorial Test Suites to Cover Input-Output Relationships
In this paper, we consider a problem that arises in black box testing: generating small test suites (i.e., sets of test cases) where the combinations that have to be covered are s...
Christine Cheng, Adrian Dumitrescu, Patrick J. Sch...
DATE
2009
IEEE
106views Hardware» more  DATE 2009»
13 years 11 months ago
Generation of compact test sets with high defect coverage
Abstract-Multi-detect (N-detect) testing suffers from the drawback that its test length grows linearly with N. We present a new method to generate compact test sets that provide hi...
Xrysovalantis Kavousianos, Krishnendu Chakrabarty
VTS
2008
IEEE
136views Hardware» more  VTS 2008»
13 years 11 months ago
Test-Pattern Grading and Pattern Selection for Small-Delay Defects
Timing-related defects are becoming increasingly important in nanometer technology designs. Small delay variations induced by crosstalk, process variations, powersupply noise, as ...
Mahmut Yilmaz, Krishnendu Chakrabarty, Mohammad Te...