14 search results - page 1 / 3 » A thread partitioning algorithm in low power high-level synt... |
ASPDAC
2004
ACM
13 years 10 months ago
2004
ACM
This paper proposes a thread partitioning algorithm in low power high-level synthesis. The algorithm is applied to high-level synthesis systems. In the systems, we can describe pa...
ICCAD
2003
IEEE
14 years 1 months ago
2003
IEEE
This work is a contribution to high level synthesis for low power systems. While device feature size decreases, interconnect power becomes a dominating factor. Thus it is importan...
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
We present a high-level synthesis algorithm solving the combined scheduling, allocation and binding problem minimizing area under both latency and maximum power per clock-cycle co...
ISSS
2000
IEEE
13 years 9 months ago
2000
IEEE
This paper addresses the problem of estimating lower bounds on the power consumption in scheduled data flow graphs with a fixed number of allocated resources prior to binding. T...
IPPS
2006
IEEE
13 years 11 months ago
2006
IEEE
Current electronic system design requires to be concerned with power consumption consideration. However, in a lot of design tools, the application power consumption budget is esti...