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» A variation tolerant subthreshold design approach
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DAC
2005
ACM
13 years 6 months ago
A variation tolerant subthreshold design approach
Nikhil Jayakumar, Sunil P. Khatri
ISLPED
2006
ACM
129views Hardware» more  ISLPED 2006»
13 years 11 months ago
Variation-driven device sizing for minimum energy sub-threshold circuits
Sub-threshold operation is a compelling approach for energyconstrained applications, but increased sensitivity to variation must be mitigated. We explore variability metrics and t...
Joyce Kwong, Anantha P. Chandrakasan
HPCA
2009
IEEE
13 years 11 months ago
Soft error vulnerability aware process variation mitigation
As transistor process technology approaches the nanometer scale, process variation significantly affects the design and optimization of high performance microprocessors. Prior stu...
Xin Fu, Tao Li, José A. B. Fortes
SOCC
2008
IEEE
169views Education» more  SOCC 2008»
13 years 11 months ago
A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies
— Lowering supply voltage is an effective technique for power reduction in memory design, however traditional memory cell design fails to operate, as shown in [3], [10], at ultra...
Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Sar...
DAC
2005
ACM
13 years 6 months ago
Mapping statistical process variations toward circuit performance variability: an analytical modeling approach
A physical yet compact gate delay model is developed integrating short-channel effects and the Alpha-power law based timing model. This analytical approach accurately predicts bot...
Yu Cao, Lawrence T. Clark