Sciweavers

18 search results - page 2 / 4
» ARC: A Self-Tuning, Low Overhead Replacement Cache
Sort
View
JSA
2006
81views more  JSA 2006»
13 years 5 months ago
Deferred locking with shadow transaction for client-server DBMSs
Data-shipping systems that allow inter-transaction caching raise the need of a transactional cache consistency maintenance (CCM) protocol because each client is able to cache a po...
Hyeokmin Kwon, Songchun Moon
DAC
2012
ACM
11 years 7 months ago
Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs
Spin-Transfer Torque RAM (STT-RAM) is an emerging non-volatile memory (NVM) technology that has the potential to replace the conventional on-chip SRAM caches for designing a more ...
Adwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, Vij...
ISCA
2011
IEEE
386views Hardware» more  ISCA 2011»
12 years 8 months ago
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs
Emerging memory technologies such as STT-RAM, PCRAM, and resistive RAM are being explored as potential replacements to existing on-chip caches or main memories for future multi-co...
Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xi...
MICRO
2010
IEEE
146views Hardware» more  MICRO 2010»
13 years 3 months ago
The ZCache: Decoupling Ways and Associativity
The ever-increasing importance of main memory latency and bandwidth is pushing CMPs towards caches with higher capacity and associativity. Associativity is typically improved by in...
Daniel Sanchez, Christos Kozyrakis
MICRO
2009
IEEE
124views Hardware» more  MICRO 2009»
13 years 11 months ago
ZerehCache: armoring cache architectures in high defect density technologies
Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly ...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...