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» ATLAS: Automatic Term-level abstraction of RTL designs
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MEMOCODE
2010
IEEE
13 years 2 months ago
ATLAS: Automatic Term-level abstraction of RTL designs
Bryan A. Brady, Randal E. Bryant, Sanjit A. Seshia...
DATE
2008
IEEE
91views Hardware» more  DATE 2008»
13 years 11 months ago
Integrating RTL IPs into TLM Designs Through Automatic Transactor Generation
Transaction Level Modeling (TLM) is an emerging design practice for overcoming increasing design complexity. It aims at simplifying the design flow of embedded systems ning and v...
Nicola Bombieri, Nicola Deganello, Franco Fummi
ICCD
2005
IEEE
165views Hardware» more  ICCD 2005»
14 years 1 months ago
Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation
Presently, Architecture Description Languages (ADLs) are widely used to raise the abstraction level of the design space exploration of Application Specific Instruction-set Proces...
Ernst Martin Witte, Anupam Chattopadhyay, Oliver S...
RSP
2003
IEEE
132views Control Systems» more  RSP 2003»
13 years 10 months ago
Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. ...
Prabhat Mishra, Arun Kejariwal, Nikil Dutt
VLSID
2004
IEEE
135views VLSI» more  VLSID 2004»
14 years 5 months ago
Integrating Self Testability with Design Space Exploration by a Controller based Estimation Technique
Recent research for testable designs has focussed on inserting test structures by re-arranging an Register-TransferLevel (RTL) data path generated from a behavioural description t...
M. S. Gaur, Mark Zwolinski