72 search results - page 1 / 15 » Abridged addressing: a low power memory addressing strategy |
ASPDAC
2006
ACM
13 years 11 months ago
2006
ACM
Abstract— The memory subsystem is known to comprise a significant fraction of the power dissipation in embedded systems. The memory addressing strategy, which determines the seq...
ASPDAC
2001
ACM
13 years 9 months ago
2001
ACM
- This paper presents encoding techniques to optimize the switching activity on a multiplexed DRAM address bus. The DRAM switching activity can be classified either as external (be...
APCCAS
2006
IEEE
13 years 11 months ago
2006
IEEE
—A pre-comparison scheme is designed by using the NOR-type 10T content addressable memory (CAM) between the match line circuits and the pre-charging circuits. Thereby, several bi...
WMPI
2004
ACM
13 years 10 months ago
2004
ACM
The size and speed of first-level caches and SRAMs of embedded processors continue to increase in response to demands for higher performance. In power-sensitive devices like PDAs a...
VLSID
2003
IEEE
14 years 5 months ago
2003
IEEE
The working-zone encoding (WZE) method employing locality of memory reference was previously proposed to reduce address bus switching activity. This paper presents an encoding met...