14 search results - page 2 / 3 » Accelerating HMMer on FPGAs using systolic array based archi... |
ICRA
1994
IEEE
13 years 9 months ago
1994
IEEE
We describe a cost-effective method for developing parallel architectures which increase the performance of range and image sensors. A parametrised edge detector and its systolic ...
IPPS
2006
IEEE
13 years 11 months ago
2006
IEEE
Diffusion Tensor Imaging (DTI) tractography in Magnetic Resonance Imaging (MRI) is a computationally intensive procedure, requiring on the order of tens of minutes to complete tr...
FPL
2006
Springer
13 years 8 months ago
2006
Springer
Field programmable gate arrays (FPGAs), graphics processing units (GPUs) and Sony's PlayStation 2 vector units offer scope for hardware acceleration of applications. We compa...
DNA
2007
Springer
13 years 8 months ago
2007
Springer
Reliable DNA computing requires a large pool of oligonucleotides that do not produce cross-hybridize. In this paper, we present a transformed algorithm to calculate the maximum wei...
ARC
2009
Springer
13 years 9 months ago
2009
Springer
Abstract. This paper presents the very first implementation of a HyperTransport 3 physical layer interface for Field Programmable Gate Arrays. HyperTransport is a low latency, high...