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DFT
1998
IEEE
129views VLSI» more  DFT 1998»
13 years 9 months ago
Accurate Fault Modeling and Fault Simulation of Resistive Bridges
Vijay R. Sar-Dessai, D. M. H. Walker
VTS
2003
IEEE
119views Hardware» more  VTS 2003»
13 years 10 months ago
A Circuit Level Fault Model for Resistive Opens and Bridges
Delay faults are an increasingly important test challenge. Traditional open and bridge fault models are incomplete because only the functional fault or a subset of delay fault are...
Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. ...
ITC
1999
IEEE
103views Hardware» more  ITC 1999»
13 years 9 months ago
Resistive bridge fault modeling, simulation and test generation
Resistive bridging faults in combinational CMOS circuits are studied in this work. Circuit-level models are ed to voltage behavior for use in voltage-level fault simulation and te...
Vijay R. Sar-Dessai, D. M. H. Walker
DATE
2008
IEEE
124views Hardware» more  DATE 2008»
13 years 11 months ago
Resistive Bridging Fault Simulation of Industrial Circuits
We report the successful application of a resistive bridging fault (RBF) simulator to industrial benchmark circuits. Despite the slowdown due to the consideration of the sophistic...
Piet Engelke, Ilia Polian, Jürgen Schlöf...
VTS
2005
IEEE
84views Hardware» more  VTS 2005»
13 years 10 months ago
Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies
We present three resistive bridging fault models valid for different CMOS technologies. The models are partitioned into a general framework (which is shared by all three models) a...
Ilia Polian, Sandip Kundu, Jean Marc Galliè...