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12

ITC
1999
IEEE

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Resistive bridge fault modeling, simulation and test generation

13 years 8 months ago

Resistive bridge fault modeling, simulation and test generation

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Resistive bridging faults in combinational CMOS circuits are studied in this work. Circuit-level models are ed to voltage behavior for use in voltage-level fault simulation and test generation. Fault simulation is done using different test sets in order to study their effectiveness. Test generation is done to detect the highest possible bridging resistance for each fault. Different test sets, power supply voltages, and fault models are studied on the ISCAS85 benchmark circuits.

Vijay R. Sar-Dessai, D. M. H. Walker

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Added	04 Aug 2010
Updated	04 Aug 2010
Type	Conference
Year	1999
Where	ITC
Authors	Vijay R. Sar-Dessai, D. M. H. Walker

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